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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
Table 5-48. Universal Serial Bus (USB) Registers (1) (continued)
CPU WORD
ADDRESS
9000h
9001h
9004h
9008h
9800h
9801h
9808h
9809h
980Ch
980Dh
9810h
9811h
9820h
9821h
9828h
9829h
982Ch
982Dh
9830h
9831h
9840h
9841h
9848h
9849h
984Ch
984Dh
9850h
9851h
9860h
9861h
9868h
9869h
986Ch
986Dh
9870h
9871h
A000h
A001h
A800h + 4 × N
A801h + 4 × N
ACRONYM
-
-
TDFDQ
DMAEMU
TXGCR1[0]
TXGCR2[0]
RXGCR1[0]
RXGCR2[0]
RXHPCR1A[0]
RXHPCR2A[0]
RXHPCR1B[0]
RXHPCR2B[0]
TXGCR1[1]
TXGCR2[1]
RXGCR1[1]
RXGCR2[1]
RXHPCR1A[1]
RXHPCR2A[1]
RXHPCR1B[1]
RXHPCR2B[1]
TXGCR1[2]
TXGCR2[2]
RXGCR1[2]
RXGCR2[2]
RXHPCR1A[2]
RXHPCR2A[2]
RXHPCR1B[2]
RXHPCR2B[2]
TXGCR1[3]
TXGCR2[3]
RXGCR1[3]
RXGCR2[3]
RXHPCR1A[3]
RXHPCR2A[3]
RXHPCR1B[3]
RXHPCR2B[3]
DMA_SCHED_CTRL1
DMA_SCHED_CTRL2
ENTRYLSW[ N ]
ENTRYMSW[ N ]
REGISTER DESCRIPTION
CPPI DMA (CMDA) Registers
Reserved
Reserved
CDMA Teardown Free Descriptor Queue Control Register
CDMA Emulation Control Register
Transmit Channel 0 Global Configuration Register 1
Transmit Channel 0 Global Configuration Register 2
Receive Channel 0 Global Configuration Register 1
Receive Channel 0 Global Configuration Register 2
Receive Channel 0 Host Packet Configuration Register 1 A
Receive Channel 0 Host Packet Configuration Register 2 A
Receive Channel 0 Host Packet Configuration Register 1 B
Receive Channel 0 Host Packet Configuration Register 2 B
Transmit Channel 1 Global Configuration Register 1
Transmit Channel 1 Global Configuration Register 2
Receive Channel 1 Global Configuration Register 1
Receive Channel 1 Global Configuration Register 2
Receive Channel 1 Host Packet Configuration Register 1 A
Receive Channel 1 Host Packet Configuration Register 2 A
Receive Channel 1 Host Packet Configuration Register 1 B
Receive Channel 1 Host Packet Configuration Register 2 B
Transmit Channel 2 Global Configuration Register 1
Transmit Channel 2 Global Configuration Register 2
Receive Channel 2 Global Configuration Register 1
Receive Channel 2 Global Configuration Register 2
Receive Channel 2 Host Packet Configuration Register 1 A
Receive Channel 2 Host Packet Configuration Register 2 A
Receive Channel 2 Host Packet Configuration Register 1 B
Receive Channel 2 Host Packet Configuration Register 2 B
Transmit Channel 3 Global Configuration Register 1
Transmit Channel 3 Global Configuration Register 2
Receive Channel 3 Global Configuration Register 1
Receive Channel 3 Global Configuration Register 2
Receive Channel 3 Host Packet Configuration Register 1 A
Receive Channel 3 Host Packet Configuration Register 2 A
Receive Channel 3 Host Packet Configuration Register 1 B
Receive Channel 3 Host Packet Configuration Register 2 B
CDMA Scheduler Control Register 1
CDMA Scheduler Control Register 1
CDMA Scheduler Table Word N Registers LSW ( N = 0 to 63)
CDMA Scheduler Table Word N Registers MSW ( N = 0 to 63)
142
Peripheral Information and Electrical Specifications
Product Folder Links: TMS320C5515
Copyright ? 2010–2013, Texas Instruments Incorporated
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